Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits

This paper reviews the circuit design considerations of scaled sub-0.1 μm partially-depleted SOI (PD/SOI) CMOS circuits for high-performance digital applications. The impact of technology/device scaling and design challenges are highlighted. Unique design aspects and issues resulting from the scaling of PD/SOI device structure, such as parasitic bipolar effect and reduced-V leakage, hysteretic V variation, low-voltage impact ionization, higher V to maintain adequate V, scaling/thinning of Si film, gate-to-body tunneling current, self-heating, soft error rate (SER), and the introduction of strained-Si channel on SOI are addressed.