A low power and high performance SOI SRAM circuit design with improved cell stability

Abstract

An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm Partially Depleted Silicon on Insulator (PD SOI) technology. The design features shorter bitlines (16 cells/bitline) along with a thin cell layout and programmable domino read operation. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability. In addition, the SRAM is supplied with multiple supplies: one to the cells, wordline drivers, and level shifters, and the other to the bitline and remaining logic to improve stability and lower power. © 2006 IEEE.