22 nm technology compatible fully functional 0.1 μm ² 6T-sram cell

Abstract

We demonstrate 22 nm node technology compatible, fully functional 0.1 μm 2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at V dd=0.9 V. We also present a 0.09 μm 2 cell with SNM of 160 mV at V dd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T- SRAM cell. Key enablers include band edge high-κ metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.