Hasan M Nayfeh

Title

Senior Research Engineer, Quantum Computing

Bio

Extensive experience in semiconductor device design in support of nanoscale CMOS technology and superconducting qubit devices for quantum computing application. Received Ph.D. degree from MIT in EECS with thesis on strained silicon device scaling. Published > 30 journal papers and awarded 9 U.S. patents with citations > 2000. Recipient of two IBM’s Outstanding Technical Achievement Awards: (1) contributions to scaling up client accessible quantum computing systems with cutting-edge performance, and (2) Two-level system monitoring and mitigation of deployed systems

Publications

Evidence for the utility of quantum computing before fault tolerance
- - Youngseok Kim
  - Andrew Eddins
  - et al.
- 2023
- Nature
Demonstration of quantum volume 64 on a superconducting quantum computing system
- - Petar Jurcevic
  - Ali Javadi-Abhari
  - et al.
- 2021
- Quantum Science and Technology
Increasing Quantum Volume on a superconducting quantum computing system
- - Petar Jurcevic
  - Ali Javadi
  - et al.
- 2021
- APS March Meeting 2021
High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Trade-offs between RF performance and total-dose tolerance in 45-nm RF-CMOS
- - Rajan Arora
  - En Xia Zhang
  - et al.
- 2011
- IEEE TNS
Impact of source/drain contact and gate finger spacing on the RF reliability of 45-nm RF nMOSFETs
- - Rajan Arora
  - Sachin Seth
  - et al.
- 2011
- IRPS 2011
Investigation of kink-induced excess RF channel noise in sub -50 nm PD-SOI MOSFETs
- - Ninad S. Wadje
  - Vijaya Bhaskara Neeli
  - et al.
- 2010
- IEEE International SOI Conference 2010
Evaluating the influence of various body-contacting schemes on single event transients in 45-nm SOI CMOS
- - Kurt A. Moen
  - Stanley D. Phillips
  - et al.
- 2010
- IEEE TNS
Impact of lateral asymmetric channel doping on 45-nm-technology N-Type SOI MOSFETs
- - Hasan M. Nayfeh
  - Nivo Rovedo
  - et al.
- 2009
- IEEE Transactions on Electron Devices
Yield monitor for embedded-SiGe process optimization
- - Xu Ouyang
  - Shwu-Jen Jeng
  - et al.
- 2008
- ICSICT 2008

Visit Google Scholar

Patents

- 17 Jun 2014
- US
- 8754446
Semiconductor Structure And Method Of Making Same
- 03 Jun 2014
- US
- 8741725
Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication
- 04 Feb 2014
- US
- 8642424
Replacement Metal Gate Structure And Methods Of Manufacture
- 12 Nov 2013
- GB
- 2497259
Fast - Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication
- 31 Jul 2013
- CN
- ZL201010212242.9
Method Of Creating Asymmetric Field-effect-transistors
- 09 Jul 2013
- US
- 8482075
Structure And Method For Manufacturing Asymmetric Devices
- 14 Dec 2012
- JP
- 5153121
Structure And Method For Reducing Miller Capacitance In Field Effect Transistors
- 31 Jul 2012
- US
- 8232151
Structure And Method For Manufacturing Asymmetric Devices
- 27 Dec 2011
- US
- 8084788
%i2p% Method Of Forming Source And Drain Of A Field-effect-transistor And Structure Thereof
- 11 Oct 2011
- US
- 8034692
Structure And Method For Manufacturing Asymmetric Devices

Top collaborators

Hasan M Nayfeh

Title

Bio

Publications

Evidence for the utility of quantum computing before fault tolerance

Demonstration of quantum volume 64 on a superconducting quantum computing system

Increasing Quantum Volume on a superconducting quantum computing system

High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization

Trade-offs between RF performance and total-dose tolerance in 45-nm RF-CMOS

Impact of source/drain contact and gate finger spacing on the RF reliability of 45-nm RF nMOSFETs

Investigation of kink-induced excess RF channel noise in sub -50 nm PD-SOI MOSFETs

Evaluating the influence of various body-contacting schemes on single event transients in 45-nm SOI CMOS

Impact of lateral asymmetric channel doping on 45-nm-technology N-Type SOI MOSFETs

Yield monitor for embedded-SiGe process optimization

Patents

Semiconductor Structure And Method Of Making Same

Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication

Replacement Metal Gate Structure And Methods Of Manufacture

Fast - Butted Soi Junction Isolation Structures And Devices And Method Of Fabrication

Method Of Creating Asymmetric Field-effect-transistors

Structure And Method For Manufacturing Asymmetric Devices

Structure And Method For Reducing Miller Capacitance In Field Effect Transistors

Structure And Method For Manufacturing Asymmetric Devices

%i2p% Method Of Forming Source And Drain Of A Field-effect-transistor And Structure Thereof

Structure And Method For Manufacturing Asymmetric Devices

Top collaborators

Lev S Bishop

Petar Jurcevic

Toshinari Itoko

Emily Pritchett