Layout-aware through-process circuit analysis
- Rama Singh
- Matt Ziegler
- et al.
- 2007
- DTIS 2007
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45 results for Matt Ziegler
Structured and tuned array generation (STAG) for high-performance random logic
- Matthew M. Ziegler
- Gary S. Ditlow
- et al.
- 2007
- GLSVLSI 2007
Multi-dimensional circuit and micro-architecture level optimization
- Qi Zhenyu
- Matthew Ziegler
- et al.
- 2007
- ISQED 2007
4th IBM IEEE CAS/EDS AI Compute Symposium (AICS'21) [CAS in the World]
- Rajiv Joshi
- Arvind Kumar
- et al.
- 2021
- IEEE Circuits and Systems Magazine
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- IEEE Journal of Solid-State Circuits
5th IBM IEEE CAS/EDS AI Compute Symposium (AICS'22) [Education]
- Rajiv Joshi
- Kaoutar El Maghraoui
- et al.
- 2023
- IEEE Circuits and Systems Magazine
Efficient AI System Design with Cross-Layer Approximate Computing
- Swagath Venkataramani
- Xiao Sun
- et al.
- 2020
- Proceedings of the IEEE
Research from the IEEE IBM AI Compute and Emerging Technology Symposia
- Matthew M. Ziegler
- Krishnan Kailas
- et al.
- 2019
- IEEE JESTCS
A Scalable Multi-TeraOPS Core for AI Training and Inference
- Sunil Shukla
- Bruce Fleischer
- et al.
- 2018
- IEEE SSC-L
Machine learning techniques for taming the complexity of modern hardware design
- Matt Ziegler
- Ramon Bertran
- et al.
- 2017
- IBM J. Res. Dev