Layout-aware through-process circuit analysis

Abstract

In the post-90nm era, due to the advent of low-K1 lithography, variability of circuit parameters, such as effective gate-length and gate-width, is increasing. In this paper, we illustrate how we perform layout aware through process circuit analysis using simulated wafer contours and present results for a full-custom 4:2 compressor circuit. © 2007 IEEE.