Publications

17 results for P. Parries

0.026μm² high performance Embedded DRAM in 22nm technology for server and SOC applications
- - C. Pei
  - G. Wang
  - et al.
- 2014
- IEDM 2014
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- - S. Narasimha
  - P. Chang
  - et al.
- 2012
- IEDM 2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- - Balaji Jayaraman
  - Sneha Gupta
  - et al.
- 2012
- ICICDT 2012
Characterization of novel TiN/HfO₂ metal insulator semiconductor stack for 32nm eDRAM
- - Puneet Goyal
  - Sneha Gupta
  - et al.
- 2010
- IEEE International SOI Conference 2010
Embedded memory considerations in SOI
- - G. Wang
  - Carl Radens
  - et al.
- 2010
- IEEE International SOI Conference 2010
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
Scaling deep trench based eDRAM on SOI to 32nm and beyond
- - G. Wang
  - D. Anand
  - et al.
- 2009
- IEDM 2009
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- - Peter J. Klim
  - John Barth
  - et al.
- 2009
- IEEE Journal of Solid-State Circuits
A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications
- - Chengwen Pei
  - Roger Booth
  - et al.
- 2008
- ICSICT 2008
Analysis of retention time distribution of embedded DRAM - A new mMethod to characterize across-chip threshold voltage variation
- - W. Kong
  - P. Parries
  - et al.
- 2008
- IEEE ITC 2008