A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
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Low-power and high-performance CMOS fingerprint sensing and encoding architecture
- Stefan Jung
- Roland Thewes
- et al.
- 1999
- IEEE Journal of Solid-State Circuits