Conference paperA 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technologyNauman Z. Butt, Kevin McStay, et al.IEDM 2010
PaperFault-tolerant designs for 256 Mb DRAMToshiaki Kirihata, Yohji Watanabe, et al.IEEE Journal of Solid-State Circuits
PaperA 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense AmplifierJohn Barth, William R. Reohr, et al.IEEE Journal of Solid-State Circuits
PaperA 14-ns 4-Mb CMOS DRAM with 300-mW Active PowerToshiaki Kirihata, Sang H. Dhong, et al.IEEE Journal of Solid-State Circuits
