Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In _0.53Ga _0.47As metal-oxide-semiconductor field-effect-transistors

Abstract

Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO 2/1 nm Al 2O 3/1 nm a-Si gate stacks on p-In 0.53Ga 0.47As/InP (001) substrates. Thanks to the presence of the Al 2O 3 barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89 nm and mid-gap interface state density of 5 × 10 11 eV -1 cm -2 upon post-metallization anneal up to 550 °C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5 nm HfO 2/1 nm Al 2O 3/1 nm a-Si gate stack and raised source and drain (600 °C for 30 min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm 2 V -1 s -1 and 740 cm 2 V -1 s -1 at carrier density of 6.5 × 10 12 cm -2) for a 1.3 nm EOT. © 2012 Crown.