The Impact of BEOL Lithography Effects on the SRAM Cell Performance and Yield

Abstract

With the feature size shrinking down to 65 nm and beyond, manufacturing process variation starts to signif cantly impact the device and interconnect electrical parameters, and therefore the performance of circuits. Back-end-of-line (BEOL) design for manufacturability concerns such as lithography variation and misalignment are more pronounced in the advanced technology node. Since SRAM cell always "tests" the most advanced technology among all design blocks, SRAM cell yield analysis considering the internal cell interconnect BEOL impact is important and necessary. In this paper, we perform a critical study of the effects of BEOL lithographic variations on SRAM performance and yield analysis. An SRAM simulation model with internal cell interconnect RC parasitics is presented in order to study the BEOL lithographic impact. With our method, the impact of BEOL variations on memory designs are systematically evaluated. First, we study the impact of ideal parasitics assuming no lithographic variations. This is followed by considering worstcase, best-case and nominal lithographic variations. On average, ideal parasitics impact the delay by more than 20-30% and impact the stability yield leading to SRAM minimum operating voltage, Vmin, increase of 100mV. This implies that the power estimation with our BEOL model is more accurate, and a traditional model without interconnect parasitic may be 33% off in terms of accuracy. Additional accounting of the litho variations for BEOL study induces about 4% variation on the SRAM read delay. Finally, when the resistance change due to misalignment is of the same order of magnitude as the nonlinear device resistance, the impact is more severe. © 2009 IEEE.