Statistical-aware designs for the nm era

Abstract

As technology scaled beyond the 100nm node, process variation and particularly random variations effects have had significant impact on the design yield. Memory designs, namely SRAMs, have become more prone to fails. Dynamic stability and dynamic noise margins have become a serious concern. Several design methodologies have been proposed to analyze and counter process variations. In this paper, we revisit key variability-driven design contributions, in terms of dual supply techniques, bitline clamping methods, and novel circuits with programmable capabilities, with particular emphasis on statistical exploration of the design space. ©2009 IEEE.