Synthesis of fully testable sequential machines

Abstract

A circuit consists of logic and memory elements. Testing of a circuit involves testing both. Typically, it takes long input sequences to initialize memory elements. Without initialization of memory elements, testing is not possible. In the classical approach to design for test, such as scan design, modifications are made to the circuit to obtain easy and full controllability and observability of the memory elements. We address the design for testability issue for non-scan designs, where both controllability and observabilities are reduced. In the process we end up with a design that is also suitable for concurrent checking. Concurrent checking is a verification process, which is performed concomitantly with normal operation. The technique described here incurs an area overhead but almost no performance penalty.