Design of TSC checkers for implementation in CMOS technology

Abstract

A fault model for CMOS digital circuits includes FET stuck-open and FET stuck-on faults, in addition to line stuck-at faults used conventionally. It has been shown that delays in CMOS circuits, under test, may invalidate tests derived by neglecting such delays. This necessitates reinvestigation of existing totally self-checking (TSC) checker designs from a new perspective. It was shown earlier that TSC checkers derived on the basis of the line stuck-at fault model for constant weight codes may not be self-testing for the CMOS fault model, violating one of the conditions of TSC circuits. A design procedure for constructing a self-testing circuit for the CMOS fault model using at most four levels is suggested. Thus previous designs can be adapted for the CMOS fault model without any penalty. The new design also makes it possible to meet arbitrary fan-in restrictions.