Timing analysis and optimization: From devices to systems

Abstract

Timing analysis spans the entire design process from RTL synthesis to timing sign-off including schematic design, logic synthesis, floor plan, place and route, clock distribution etc. In this embedded tutorial we will cover timing analysis from devices to systems. At the transistor level we will cover static, dynamic and interconnect analysis. At the gate level we will cover path analysis including false paths and static and dynamic sensitization aspects. The new Delay Calculator Language (DCL) will also be covered. We will tie the statistical properties at each level to put them under proper perspective.