Sub-Thermionic Scalable III-V Tunnel Field-Effect Transistors Integrated on Si (100)

Abstract

We present scalable III-V heterojunction tunnel FETs fabricated using a Si CMOS-compatible FinFET process flow and integrated on Si (100) substrates. The tunneling junction is fabricated through self-aligned selective p+ GaAsSb raised source epitaxial regrowth on an InGaAs channel. Similarly, the drain is formed by an n+ InGaAs regrowth. The Si CMOS-compatible fabrication process includes a self-aligned replacement metal gate module, high-k/metal gate, scaled device dimensions and doped extensions, enabling high junction alignment accuracy. The devices exhibit a minimum subthreshold slope of 47 mV/decade, an ION of 1.5 μA/μm at IOFF = 1 nA/μm and VDD = 0.3 V, and I60 of 10 nA/μm. This is the first demonstration of sub-60 mV/decade switching in heterostructure TFETs on Si (100), showing the strong promise of the technology for future advanced logic nodes aiming at low-power applications.