A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations. © 1963-2012 IEEE.
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
Jae-Sun Seo, Bernard Brezzo, et al.
CICC 2011
Bipin Rajendran, Matt Breitwisch, et al.
IEEE Electron Device Letters
Byungsub Kim, Yong Liu, et al.
IEEE Journal of Solid-State Circuits