RF potential of a 0.18-μm CMOS logic device technology

Abstract

The radio-frequency (rf) performance of a 0.18-μm CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies (fT, and fmax), the minimum noise figure (Fmin) and associated power gain (Ga), and the 1/f-noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the rf performance without any technology process modifications. Changing to N2O gate dielectrics is shown to greatly reduce the 1/f noise without sacrificing the ac performance. The power amplifier characteristics of CMOS at low power levels are also discussed.