Porous ILD process development for sub 100nm integration

Abstract

Due to the miniaturization of device features below 0.1μm, it has become necessary for the semiconductor industry to build denser chips within equivalent or smaller areas using Ultra-Low-k (ULK) materials (1.5<k<2.6). The use of ULK materials ensures that the stringent RC delay and performance requirements listed in the 2001 Interconnect Technology Roadmap for Semiconductors (ITRS) 1 will be met. A variety of these ULK materials, namely porous materials have been evaluated by IBM, and demonstrate the mechanical integrity to withstand single and dual-damascene integration. In this communication, we report specifically on the integration of porous SiLK™ and JSR 5109 (porous OSG). © 2004 Materials Research Society.