Conference paper
Pushing ASIC performance in a power envelope
Ruchir Puri, Leon Stok, et al.
DAC 2003
Integrated logic synthesis and physical design (physical synthesis) continues to play a very important role in high performance microprocessor design methodologies, In this paper, we present the integrated physical synthesis timing closure methodology used in the current generation microprocessors. Physical synthesis techniques were aggressively used as part of logic and placement optimizations for performance, power and area. The design turn around times were significantly reduced and timing convergence was consistently acheived.
Ruchir Puri, Leon Stok, et al.
DAC 2003
Nana B. Sam, Sally A. McKee, et al.
ICECS 2006
D. Goren, M. Zelikson, et al.
DAC 2003
Rupesh Raj Karn, Prabhakar Kudva, et al.
IEEE TPDS