On the performance and scaling of symmetric lateral bipolar transistors on SOI

Abstract

The performance potential and scaling characteristics of thin-base SOI symmetric lateral bipolar transistors were examined using 1-D analytic equations for the currents and capacitances. The device can operate at collector current densities < 100 mA/μm2, and it scales similarly to CMOS in terms of density. The physical base width is scalable to less than 20 nm. Multiple devices of different specifications can be integrated on a chip. A sample design is shown to have fT < 200 GHz, fmax < 1 THz, VA <4V, and a self gain of 60. A balanced design is shown to have 350-GHzfT and 700-GHzfmax, VA of 2.4V, and a self gain of 20. These results are superior to those reported for 32nm SOI CMOS. The results suggest a need to rethink bipolar circuit design. They also suggest opportunities for novel bipolar and BiCMOS circuits. The devices in high-speed Si-base bipolar circuits operate at about 1.0V. The path toward 0.5V bipolar circuits is to use semiconductors with smaller bandgap, such as Ge.