The Design and Electrical Characteristics of High-Performance Single-Poly Ion-Implanted Bipolar Transistors

Abstract

This paper describes the design, electrical characteristics, and performance of single-poly (poly emitter) bipolar transistors. A low-resistance ion-implanted extrinsic base is realized; the sheet resistance is 85 Ω/□ and the junction depth is 0.3 μm. A self-aligned profile scheme is implemented to place the heavily doped extrinsic base region 0.2 μm away from the emitter. Similar to the LDD profile in MOSFET's, a link region of medium implant dose is formed to bridge the intrinsic base and the extrinsic base, and also to buffer the heavily doped emitter and extrinsic base. The silicon surface is not etched throughout the process, and the surface remains planar during the intrinsic base process to facilitate the formation of a very shallow vertical profile. A base width of 105 nm has been obtained. Experimental hardware shows that, at 0.8-μm design rules, the ft of transistors reaches 16 GHz and the gate delay of the ECL circuits reaches the sub-50-ps range, thus demonstrating the performance potential of single-poly transistors. With an optimized link, the E-B junction breakdown and C-E punchthrough characteristics are no longer affected by the extrinsic base and correlate well with the intrinsic-base implant. As a result, both high-voltage analog and low-voltage high-speed logic devices can be built on the same chip by applying different implant conditions. The scaling of the single-poly bipolar transistor is more straightforward due to its simpler structure and lower topography. It readily lends itself to high-performance BiCMOS applications. © 1989 IEEE