Conference paper
State-based power analysis for systems-on-chip
Reinaldo A. Bergamaschi, Yunjian W. Jiang
DAC 2003
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Reinaldo A. Bergamaschi, Yunjian W. Jiang
DAC 2003
Martin Ohmacht, Reinaldo A. Bergamaschi, et al.
IBM J. Res. Dev
Hiren D. Pate, Sandeep K. Shukla, et al.
DATE 2006
Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems