Abstract
In high-level synthesis, the generation of different designs is generally referred to as design space exploration. This paper presents an efficient and accurate method for design space exploration based on redesign. Initially, a design that optimizes a design criterion such as performance is synthesized. State splitting then successively generates new designs by introducing additional control states. The size of each design is accurately estimated using a tentative data-path allocation and then computing its area using a typical CMOS cell library implementation. Results for six benchmark examples illustrate these techniques.