New polysilicon disposable sidewall process for sub-50 nm CMOS

Abstract

A novel disposable polysilicon/RTCVD nitride sidewall process for sub-50 nm CMOS has been developed. This process allows the gate and deep source drain doping and anneals to be performed before the shallow extension and halo, thus enabling independent optimization of gate activation and low-thermal-cycle abrupt junctions. The new process offers much higher etch selectivities in terms of sidewall formation and strip operations than the oxide and nitride sidewall processes. In addition, it also gives much better sidewall dimensional control for device optimization. Sub-100 nm device fabricated with disposable sidewall process show less poly depletion (thinner Tinv) and significantly improved drive current than those fabricated with the conventional process. A high transconductance of 1150 mS/mm is obtained with the shortest device of 32 nm gate length generated by the new disposable polysilicon sidewall process.