About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEDM 1999
Conference paper
Very high performance 50 nm CMOS at low temperature
Abstract
An account is given on very high performance CMOS devices with 50 nm channel lengths on 1.7 nm gate oxide. These devices are suitable for low temperature operation. The devices are shown to represent the highest CMOS performance reported to date.