70 nm damascene-gate MOSFETs with minimal polysilicon gate-depletion

Abstract

In this work, for the first time, we present very high performance CMOS devices with 70 nm gate length and 2.2 nm Tinv effective gate oxide thickness fabricated using a damascene-gate process. Poly-Si gate electrodes are used with minimal poly depletion due to the de-coupling of the gate implantation from the source and drain implantation in the damascene-gate process. Saturation transconductance of 722 μS/μm for nMOSFETs and 354 μS/μm for pMOSFETS are achieved. ION for a 1.5 V supply is 0.9 mA/um for the nMOSFETs and 0.43 mA/um for the pMOSFETs with IOFF of both devices is 20 nA/um. The reduced junction capacitance and minimal poly-Si gate depletion in the damascene process resulted in a measured delay per stage of 8.6 ps for a 101-stage CMOS inverter ring oscillator at 1.5 V supply.