Bruce Doris, B. Desalvo, et al.
Solid-State Electronics
Conference paper
Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance
Abstract
This paper analyses the impact of 10nm Si cap layer for UTBB pFET eSiGe, with 35% Ge in channel and source/drain. For the first time, it is found that this Si cap can improve both access resistance and hole mobility in narrow structures.
Related
S. Reboh, R. Coquand, et al.
Applied Physics Letters
F. Allibert, Pierre Morin, et al.
S3S 2014
Joshua Rubin, Kevin Winstel, et al.
S3S 2015