High performance metallization issues for ULSI

Abstract

The microelectronics industry is accelerating towards increasingly sophisticated circuit technology to interface with and drive a wide spectrum of products from low power to supercomputation systems. The base Si CMOS technology will span the applications such that optimization must be achieved by personalized wiring for each industry sector. As the feature size decreases to 0.25 μm or less, the interconnect metallization becomes a dominant technological challenge as circuit speeds, reliability and manufacturing costs are directly affected. The label 'high performance' must now be defined in the context of the application. For example, as scaling proceeds for increased density and circuit speed, current density increase will impact lifetime by electromigration. Methods of simulation of fundamental degradation modes and design software tools must be developed and used in concert with performance simulation to optimize interconnect metallization ground rules early in the development cycle. Availability of such tools for interconnects is practically nonexistent, spurring significant focus on this direction by the materials community.