About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
VLSI Technology 2000
Conference paper
High performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
Abstract
The fabrication of a high performance 0.13 μm SOI logic technology with copper BEOL and advanced low-k dielectric is demonstrated using 248 nm lithography for all critical levels. The interconnect performance requirements are met by using a 8 level copper BEOL with an advanced low-k dielectric. This technology supports an SRAM cell size of 2.16 μm2, the smallest reported to date.