About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Conference paper
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
Abstract
We report a high-performance CMOS operating at 1.5 V with 11.9 ps nominal inverter delay at 0.06/0.08 μm Leff for NMOS and PMOS. Both NMOS and PMOS devices, with 3.6 nm inversion Tox, have the best current drive reported to date at fixed Ioff. Low-Vt NMOS/PMOS achieved with compensation and with no degradation in short-channel behavior result in nominal 9.7 ps inverter delay. These devices are incorporated in a 0.18 μm technology that offers a 4.2 μm2 SRAM cell and dual gate oxide for interfacing to 2.5 V.