Stable SRAM cell design for the 32 nm node and beyond
Leland Chang, David M. Fried, et al.
VLSI Technology 2005
In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of tie electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-/μm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved. © 1984 IEEE
Leland Chang, David M. Fried, et al.
VLSI Technology 2005
Jack Y.-C. Sun, Matthew R. Wordeman, et al.
IEEE T-ED
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Solid-State Electronics
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IEEE Journal of Solid-State Circuits