Fully Automated Thermal Scanning Probe Lithography for FET Batch Fabrication

Abstract

Thermal Scanning Probe Lithography has become a successful, commercially available tool for the fabrication of nanoscale devices. The growing maturity of the technology is reflected in the increasing number of publications originating from users around the globe. In particular, the unique technology aspects such as nanometer accurate grayscale patterning and low damage patterning of high-resolution structures has fueled this success. In this talk I will give a brief overview over the technology and its accomplishments. I will focus on some key results from IBM and external groups and explain how the tool capabilities enabled these achievements. The work covers a range of application from nanofluidic Brownian motors [1] to optical Fourier series [2] and low contact resistances for 2D material devices [3]. In addition to this growing success, the tool has potential in many areas for further innovation. For a widespread use in the research environment and for first manufacturing applications, the reliability, endurance, and throughput must be improved. Recently, we made significant progress in this direction. A key enabler was the highly improved resist material that is now commercially available. For grayscale pattern fabrication, it allows for several days of continuous patterning with a single tip. For high resolution patterning, it enables the fabrication of multiple chips with a single tip. We showcase the potential of the tool by fabricating arrays of field effect transistors on SOI substrates. All the lithographical steps are done by the tSPL tool, assisted by the integrated laser writer [4]. The field effect transistors have a channel width between 15 and 50 nm. Gates of similar size are patterned using a markerless overlay approach. The algorithm extracts the device geometry from the programmed pattern and correlates it with the observed topography. This alignment procedures optimizes the overlay at the critical position where the gate and the fin meet and allows for a fully automated process over the chip area. I will discuss the statistical variations in the observed device dimensions and overlay accuracies. This work is a first step for tSPL to develop towards a high precision, fully automated lithography tool. Considering the relative ease of implementing parallel concepts with cantilevers, we see an exciting future for the technology. [1] M. J. Skaug et al. “Nanofluidic rocking Brownian motors” Science. 359, 6383, 1505–1508, 2018. [2] N. Lassaline et al. “Optical Fourier surfaces” Nature 582, 7813, 506–510, 2020. [3] X. Zheng et al. “Patterning metal contacts on monolayer MoS 2 with vanishing Schottky barriers using thermal nanolithography” Nature Electronics 2, 1, p. 17, 2019. [4] C. D. Rawlings et al. “Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing” Nanotechnology 29, 50, 505302, 2018.