FinFET resistance mitigation through design and process optimization

Abstract

The intrinsic FinFET device structure can provide an estimated 10-20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um. ©2009 IEEE.