Experimental low temperature DRAM

Abstract

The authors present comprehensive performance measurements on a low-temperature very high-speed DRAM (dynamic RAM). It is shown that a significant speed improvement for CMOS DRAMs can be obtained by low-temperature operation, even without device optimization for the low-temperature environment. The speed improvement over conventional DRAMs that is obtained with the high-speed DRAM concept is quite dramatic. Even with a nonoptimum 1.0-μm technology, 12-ns 512K low-temperature DRAM operation was achieved. Soft error rates (SERs) for low-temperature operation are reported, and it is demonstrated that noise, SER, and power do not preclude very high-speed LN2 DRAM operation. Retention time was greatly enhanced at low temperature, with no evidence of early failures.