An 11 Gb/s 2.4 mW half-rate sampling 2-tap DFE receiver in 65nm CMOS

Abstract

A 2-tap DFE receiver, implemented in a standard digital 65nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22mW/Gbps power/speed ratio of the receiver and core area of 30μm × 40μm are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s (2.6mA from 0.9V supply), the BER is less than 10-14 with a PRBS7 test sequence passing through a 30" channel (15dB of loss at 5.5GHz).