PaperDecomposition and analysis of process variability using constrained principal component analysisOngyeun Cho, Daeik D. Kim, et al.IEEE Trans Semicond Manuf
Conference paperA 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrierBodhisatwa Sadhu, Mark A. Ferriss, et al.RFIC 2012
PaperA 250-mW 60-GHz CMOS Transceiver SoC Integrated with a Four-Element AiP Providing Broad Angular Link CoverageBodhisatwa Sadhu, Alberto Valdes-Garcia, et al.IEEE JSSC
Conference paperDouble-gate FET technology for RF applications: Device characteristics and low noise amplifier designKaran Bhatia, Keunwoo Kim, et al.IEEE SOI 2006