A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS

Abstract

A 32kb subarray demonstrates practiedl implementation of a 65nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41V at 295MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8T cell, 5.3GHz operation at 1.2 V is achieved.