Conference paper
23 ps/2.1 mW ECL gate
Kai-Yap Toh, C.T. Chuang, et al.
ISSCC 1989
The Letter describes the first experimental result of a high-speed low-power ECL-based AC-coupled complementary push-pull circuit. Implemented in a 0.8µm high-performance fully complementary bipolar technology with 50GHz npn transistor and 13GHz pnp transistor, a power-delay product of 34fJ (23.2ps at 1.48mW) has been achieved compared with 67 fJ (45 ps at 1.48mW) for the npn-only ECL circuit. © 1993, The Institution of Electrical Engineers. All rights reserved.
Kai-Yap Toh, C.T. Chuang, et al.
ISSCC 1989
J. Warnock, D.D. Awschalom, et al.
Physical Review B
C.T. Chuang
IEEE International SOI Conference 1998
B.S. Wu, C.T. Chuang, et al.
IEEE Transactions on Electron Devices