Conference paper
Novel circuits to improve SRAM performance in PD/SOI technology
R.V. Joshi, A.J. Bhavnagarwala, et al.
IEEE International SOI Conference 2001
Paper
AC-coupled complementary push-pull ECL circuit with 34 fJ power-delay product
Abstract
The Letter describes the first experimental result of a high-speed low-power ECL-based AC-coupled complementary push-pull circuit. Implemented in a 0.8µm high-performance fully complementary bipolar technology with 50GHz npn transistor and 13GHz pnp transistor, a power-delay product of 34fJ (23.2ps at 1.48mW) has been achieved compared with 67 fJ (45 ps at 1.48mW) for the npn-only ECL circuit. © 1993, The Institution of Electrical Engineers. All rights reserved.