Mohamed R. Abdelhamid, Arun Paidimarri, et al.
CICC 2018
A buck converter in 65-nm CMOS is optimized for a low quiescent power of 240 pW. It operates with input 1.2-3.3 V and regulates the output from 0.7-0.9 V. Control circuits are designed for low leakage and static current, and scale in power over a hertz to megahertz frequency range, resulting in a wide load current dynamic range of 2× 10-6. With a 2-V input, the converter has a peak efficiency of 89% and delivers load currents of 500 pA to 1 mA with efficiency better than 50%. The peak efficiency is 92% for a 1.2-V input.
Mohamed R. Abdelhamid, Arun Paidimarri, et al.
CICC 2018
Mohamed R. Abdelhamid, Arun Paidimarri, et al.
CICC 2018
Arun Paidimarri, Bodhisatwa Sadhu
RFIC 2020
Ramon Bertran, Pradip Bose, et al.
ICCD 2017