Sameh Asaad, Ralph Bellofatto, et al.
FPGA 2012
This brief describes a low-power full-rate semi-digital delay-locked loop,(DLL) architecture using an analog-based finite state machine,(AFSM) and a polyphase filter. The AFSM architecture uses low-power analog blocks to map high-frequency loop feedback information to low frequency, thus reducing the total power required for digital signal processing and for the macro as a whole. The polyphase filter generates full-rate multiphase outputs for a phase rotator, hence a reference clock of the semi-digital DLL can be generated by any reference source including a phase-locked loop with an LC voltage-controlled oscillator. The prototype semidigital DLL in 0.12-μm CMOS exhibits less than 10-12 bit error rate at 3.2 Gb/s consuming 60 mW. © 2004, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Sameh Asaad, Ralph Bellofatto, et al.
FPGA 2012
Woogeun Rhee, Herschel Ainspan, et al.
CICC 2003
Babak Soltanian, Herschel Ainspan, et al.
CICC 2006
Jean-Olivier Plouchart, Mark A. Ferriss, et al.
CICC 2012