Mounir Meghelli, Alexander V. Rylyakov, et al.
IEEE Journal of Solid-State Circuits
A per-core clock generator for the eight-core POWER7™ processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques. © 2010 IEEE.
Mounir Meghelli, Alexander V. Rylyakov, et al.
IEEE Journal of Solid-State Circuits
Alexander Rylyakov, Thomas Zwick
IEEE Journal of Solid-State Circuits
Matt Park, John Bulzacchelli, et al.
ISSCC 2007
Bodhisatwa Sadhu, Mark A. Ferriss, et al.
RFIC 2012