A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization

Abstract

A 4.9 to 6.4Gb/s 2-level SerDes ASIC I/O core designed in 0.13μm CMOS uses a 4-tap FFE in the transmitter and a 5-tap DFE with receiver AGC. Error-free operation is achieved on channels with over 30dB loss at the half-baud rate. The TX/RX pair consumes 290mW from a 1.2V supply and uses a die area of 0.79mm 2. © 2005 IEEE.