John D. Cressler, James Warnock, et al.
IEEE Electron Device Letters
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
John D. Cressler, James Warnock, et al.
IEEE Electron Device Letters
Joachim N. Burghartz, Jean-Olivier Plouchart, et al.
IEEE Electron Device Letters
Keith A. Jenkins, Alan J. Weger
IEEE Electron Device Letters
James Warnock, John D. Cressler, et al.
IEEE Electron Device Letters