Publications

112 results for S.L. Wright

Characterization of stacked die using die-to-wafer integration for high yield and throughput
- - K. Sakuma
  - P. Andry
  - et al.
- 2008
- ECTC 2008
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
- - Paul S. Andry
  - Cornelia K. Tsang
  - et al.
- 2008
- IBM J. Res. Dev
3D chip stacking with C4 technology
- - Bing Dang
  - Steven L. Wright
  - et al.
- 2008
- IBM J. Res. Dev
3D chip-stacking technology with through-silicon vias and low-volume lead free interconnections
- - Katsuyuki Sakuma
  - Paul S. Andry
  - et al.
- 2008
- IBM J. Res. Dev
Three-dimensional silicon integration
- - John U. Knickerbocker
  - Paul S. Andry
  - et al.
- 2008
- IBM J. Res. Dev
3D chip stacking technology with low-volume lead-free interconnections
- - K. Sakuma
  - P. Andry
  - et al.
- 2007
- ECTC 2007
Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-package
- - B. Dang
  - S.L. Wright
  - et al.
- 2007
- ECTC 2007
A CMOS-compatible process for fabricating electrical through-vias in silicon
- - P. Andry
  - C. Tsang
  - et al.
- 2006
- ECTC 2006
Characterization of micro-bump C4 interconnects for Si-carrier SOP applications
- - S.L. Wright
  - R.J. Polastre
  - et al.
- 2006
- ECTC 2006
Pb-free micro-joints (50 μm pitch) for the next generation micro-systems: The fabrication, assembly and characterization
- - H. Gan
  - S.L. Wright
  - et al.
- 2006
- ECTC 2006