RaPiD: AI Accelerator for Ultra-Low Precision Training and Inference
- Swagath Venkataramani
- Vijayalakshmi Srinivasan
- et al.
- 2021
- ISCA 2021
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13 results for Ching Zhou
A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- ISSCC 2024
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling
- Ankur Agrawal
- Saekyu Lee
- et al.
- 2021
- ISSCC 2021
Row based dual-vdd island generation and placement
- Hua Xiang
- Haifeng Qian
- et al.
- 2014
- DAC 2014
A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- Sae Kyu Lee
- Ankur Agrawal
- et al.
- 2021
- IEEE JSSC
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
- Jinwook Oh
- Sae Kyu Lee
- et al.
- 2020
- VLSI Circuits 2020
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and Inference
- Bruce Fleischer
- Sunil Shukla
- et al.
- 2018
- VLSI Circuits 2018
Synthesis design strategies for energy-efficient microprocessors
- Ching Zhou
- Yu-Shiang Lin
- et al.
- 2016
- ICCD 2016
Gate movement for timing improvement on row based Dual-VDD designs
- Hua Xiang
- Lakshmi Reddy
- et al.
- 2016
- ISQED 2016
64-bit prefix adders: Power-efficient topologies and design solutions
- Ching Zhou
- Bruce M. Fleischer
- et al.
- 2009
- CICC 2009