A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications
- Win-San Khwa
- Meng-Fan Chang
- et al.
- 2017
- IEEE JSSC
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75 results for Matthew BrightSky
A Retention-Aware multilevel cell phase change memory program evaluation metric
- Win-San Khwa
- Meng-Fan Chang
- et al.
- 2016
- IEEE Electron Device Letters
As-Se-Ge-S and Ge-N Heterostructures for Superior OTS Performance
- Alexander Grun
- Zhi-Lun Liu
- et al.
- 2024
- IMW 2024
A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications
- W. Chien
- E. Lai
- et al.
- 2023
- IMW 2023
Endurance Evaluation on OTS-PCM Device using Constant Current Stress Scheme
- W. Chien
- Lynne Gignac
- et al.
- 2022
- IRPS 2022
Device Study on OTS-PCM for Persistent Memory Application : IBM/Macronix Phase Change Memory Joint Project
- W. Chien
- Lynne Gignac
- et al.
- 2022
- EDTM 2022
Accurate weight mapping in a multi-memristive synaptic unit
- Michele Martemucci
- Benedikt Kersting
- et al.
- 2021
- ISCAS 2021
Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation
- Robert L. Bruce
- Syed Ghazi Sarwat
- et al.
- 2021
- IRPS 2021
A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM
- Nanbo Gong
- W. Chien
- et al.
- 2020
- VLSI Technology 2020
Si Incorporation Into AsSeGe Chalcogenides for High Thermal Stability, High Endurance and Extremely Low Vth Drift 3D Stackable Cross-point Memory
- Huai-Yu Cheng
- I. Kuo
- et al.
- 2020
- VLSI Technology 2020