A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
Publications
5 results for Johann Alsmeier
0.21 μm2 7F2 trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
- C. Radens
- U. Gruening
- et al.
- 1998
- VLSI Technology 1998
DRAM technologies for today's market and future DRAM generations
- W. Neumueller
- J. Alsmeier
- et al.
- 1997
- ESSDERC 1997
Anomalous Narrow Channel Effect in Trench-Isolated Buried-Channel P-MOSFET‘s
- J.A. Mandelman
- J. Alsmeier
- 1994
- IEEE Electron Device Letters
A 0.6 µm2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)
- L.A. Nesbit
- J. Alsmeier
- et al.
- 1993
- IEDM 1993