Virtual de-embedding study for the accurate extraction of Fin FET gate resistance

Abstract

Accurate measurement of FET gate resistance is needed to support technology development and to understand its impact on RF performance. This is especially true for high-K Metal Gate Fin FET technologies. Decreasing gate capacitance with each successive technology node has made gate resistance measurement increasingly difficult. This work presents a 'Virtual De-Embedding' approach to the optimization of gate resistance measurement structures and de-embedding methodologies. This optimization was done without needing to fabricate multiple test structure variations to determine the optimal structure. We examine the effects of back-end-of-line (BEOL) stack, groundplane design, FET size, and de-embedding technique on gate resistance measurement accuracy.