RF modeling of 45nm low-power CMOS technology

Abstract

In this paper, we present an advanced RF modeling work for our state-of-the-art 45nm low-power CMOS technology. Based on carefully designed structures, we extracted a rigorous, hardware-based wiring capacitance model that accurately computes each component of the wirecap network on top of the intrinsic FET. A novel, scalable substrate resistance model was created to well fit relevant hardware data. To obtain accurate on-wafer s-parameter data for the modeling structures at high frequencies (up to 110GHz), we adopted sophisticated deembedding techniques such as Pad-Open-Short and COMPLETE. The results clearly show that our models well match various RF characteristics for devices with a broad range of sizes and measured at different voltage biases. Undoubtedly, these high-quality RF FET models offer circuit designers an indispensable and powerful tool to best utilize our advanced RFCMOS technology.